Designing with an Intel ARM SoC

Co-Design and Co-Debug on Intel (Altera) RM-based SoC FPGA.

  HOME >> Courses and Training >> Designing with an Intel ARM SoC

VEC221E: Designing a SOM with an Intel ARM SoC Fpga

Fpga training series

FPGA ARM SOC Training, how to build a FPGA SOM Module using Linux Or Android OSThe Intel® ARM SOC course is composed of two sessions, the first is mainly dedicated to the hardware, the second one will explore the software aspects paying special  attention to the OS boot process, including also linux boot.

 

VEC2210E, hardware session.

In this Fpga training you’ll learn to design for a system containing the ARM® Cortex-A9 Hard Processor System (HPS) on Cyclone® and  Arria® SoCs. This course focuses on the hardware aspects of designing the SoC system & includes hands-on labs to get you up & running quickly.

 

Learn to add & configure the processor component into a Qsys system. You’ll perform debug of the hardware system using standard debug tools such as SignalTap II logic analyzer & System Console.

 

We’ll discuss hardware to software files handoff that simplifies aspects of software development. You’ll perform low-level debug of the FPGA interacting with the software debugger.

 

We’ll also discuss various ways the FPGA & HPS components can be loaded & booted. At completion, you’ll be able to use the SoC device in your own design.

 

At Session Completion You will be able to:

  • Create, manage, and compile an SoC based FPGA in the Qsys tool
  • Simulate the HPS interfaces using Qsys testbench and simulation model generation features
  • Bring up and debug an SoC with the System Console tool
  • Explain the hardware to software file handoff
  • Design and debug with a Cyclone V based development kit

 

VEC2211E: This FPGA course is for firmware and low-level software engineers and is intended to teach you about software bring-up and development on the embedded ARM® Cortex-A9 hard processor system (HPS) in an SoC

 

The course isn’t intended to teach you software application or driver development, but rather concentrates on the unique aspects of the embedded HPS software flow in an Intel® ARM®-SoC.

 

You’ll learn everything needed to get started developing software for the HPS system, where to go for additional help, as well as how to use the Intel® (Altera®) edition of the ARM DS-5 software development tool to debug your software.


At Session Completion You will be able to:

  • Explain the hardware-to-software file handoff
  • Explain the stages in the HPS boot sequence & the boot scenarios
  • Create the second-state bootloader
  • Write bare-metal applications using Intel®’s Hardware Libraries
  • Get started with a variety of OSs for the ARM processor
  • Get support from the community portal on Linux development
  • Use DS-5 development studio to perform FPGA-adaptive software debug

 

Prerequisites and Skills Required

  • Completition of the training VEC110, System Integration with Qsys
  • FPGA knowledge is not required, but a plus
  • Some basic software knowledge and C/C++ coding skills are required

Geb Enterprise Online Shop-VEC221E: Intel® SOC HW/SW Training

-VEC2212E: Bundle, Intel® Soc board including HW/SW Trainig.

 

Note: All brand names or product names mentioned are trademarks or registered trademarks of their respective owners

 

 

GEB Enterprise S.r.l. • VAT 10190271006
Via Rocca di Papa, 21 - 00179 Roma ITALY •
Ph. +39 06 7827464 - Fax: +39 06 7806894 • info@geb-enterprise.com
web-design

Copyright © 2009 GEB Enterprise S.r.l. All rights reserved.


FEED RSS2.0